publications

Publications

Journal :

S. Srivastava and S. Bhanja, "Integrating Nano-logic Knowledge Module into an Undergraduate Logic Design Course", Accepted for publication at IEEE Transactions on Education, 2008.

V. Mahalingam, N. Ranganathan and J.E. Harlow, "A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing", Accepted for publication at IEEE Transactions on VLSI Systems, 2008.

Koustav Bhattacharya, Nagarajan Ranganathan and Soontae Kim, "A Framework For Correction of Multi-bit Soft Errors in L2 Caches Based on Redundancy", Accepted for publication at IEEE Transactions on VLSI Systems, 2008.

V. Mahalingam and N. Ranganathan, "Timing Based Placement Considering Uncertainty due to Process Variations", Submitted at IEEE Transactions on VLSI Systems, 2008.

Hao Zheng, Jared Ahrens and Tian Xia, "A Compositional Method with Failure-Preserving Abstraction for Asynchronous Design Verification", Accepted for publication at IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, 2008.

T. Rejimon and S. Bhanja, "Probabilistic Error Model for Nano-Domain Logic Circuits", Accepted for publication at IEEE Transactions on VLSI Systems, 2007.

S. Bhanja and S. Sarkar, "Thermal Switching Error versus Delay Tradeoffs in Clocked QCA Circuits", Accepted for publication at IEEE Transactions on VLSI Systems, 2007.

Conference :

H. Sakaran and S. Katkoori, "Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis", Accepted for publication at International Symposium on VLSI, 2008.

H. Sankaran and S. Katkoori, "Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis", Accepted for publication at IEEE International Symposium on Electronic Design, Test, and Applications (DELTA), 2008.

Koustav Bhattacharya and Nagarajan Ranganathan, "Reliability-centric Gate Sizing with Simultaneous Optimization of Soft Error Rate, Delay and Power", Submitted at ISLPED, 2008.

V. Mahalingam and N. Ranganathan, "A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing", Accepted for publication at the Proceedings of ISVLSI, 2008.

N. Ranganathan, U. Gupta and V. Mahalingam, "Simultaneous Optimization of Total Power, Crosstalk Noise and Delay Under Uncertainty", Accepted for publication at the Proceedings of GLSVLSI, 2008.

Koustav Bhattacharya and Nagarajan Ranganathan, "A Linear Programming Formulation for Security-Aware Gate Sizing", Accepted for publication at the Proceedings of GLSVLSI, 2008.

V. K. Jain, and E. E. Swartzlander, Jr., " 32 Bit Single Cycle Nonlinear VLSI Cell for the ICA Algorithm", Accepted for publication at the Proceedings of International Conference on Acoustics Speech and Signal Processing, 2008.

Disclaimer: This material is based upon work supported by the National Science Foundation under Grant No. 0551621.